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1 ? fn8086.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) and xdcp are registered trademarks of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. ISL90840 quad digitally controlled potentiometers (xdcp?) low noise, low power i 2 c ? bus, 256 taps the ISL90840 integrates fo ur digitally controlled potentiometers (xdcp) on a monolithic cmos integrated circuit. the digitally controlled potenti ometers are implemented with a combination of resistor elements and cmos switches. the position of the wipers are contro lled by the user through the i 2 c bus interface. each potentiometer has an associated wiper register (wr) that can be directly written to and read by the user. the contents of t he wr controls the position of the wiper. the dcps can be used as three-terminal potentiometers or as two-terminal variable resistors in a wide variety of applications including control, parameter adjustments, and signal processing. features ? four potentiometers in one package ? 256 resistor taps - 0.4% resolution ?i 2 c serial interface - three address pins, up to eight devices/bus ? wiper resistance: 70 ? typical @ 3.3v ? standby current <5a max ? power supply: 2.7v to 5.5v ?50k ? , 10k ? total resistance ? 20 lead tssop ? pb-free plus anneal available (rohs compliant) functional diagram ordering information part number package temp range (c) resistance option ( ? ) ISL90840uiv2027 20 ld tssop -40 to +85 50k ISL90840uiv2027z (notes 1 & 2) 20 ld tssop (pb-free) -40 to +85 50k ISL90840wiv2027 20 ld tssop -40 to +85 10k ISL90840wiv2027z (notes 1 & 2) 20 ld tssop (pb-free) -40 to +85 10k notes: 1. intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb- free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 2. contact factory for availability. pinout ISL90840 (20 lead tssop) top view rw0 rl0 rh0 d.n.c. vcc a1 a0 rh1 rl1 rw1 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 rh3 rl3 rw3 a2 scl sda gnd rw2 rl2 rh2 i 2 c interface v cc r h0 r h1 r h2 r h3 gnd r l0 r l1 r l2 r l3 r w0 r w1 r w2 r w3 scl sda a0 a1 a2 data sheet july 27, 2005
2 fn8086.0 july 27, 2005 block diagram wr3 wr2 wr1 wr0 dcp3 dcp2 dcp1 dcp0 r h3 r w3 r l3 r h2 r w2 r l2 r h1 r w1 r l1 r h0 r w0 r l0 power-up, interface, control and status logic i 2 c interface sda scl a2 a1 a0 gnd v cc pin descriptions tssop pin symbol description 1 rh3 ?high? terminal of dcp3 2 rl3 ?low? terminal of dcp3 3 rw3 ?wiper? terminal of dcp3 4 a2 device address for the i 2 c interface 5scli 2 c interface clock 6 sda serial data i/o for the i 2 c interface 7 gnd device ground pin 8 rw2 ?wiper? terminal of dcp2 9 rl2 ?low? terminal of dcp2 10 rh2 ?high? terminal of dcp2 11 rw1 ?wiper? terminal of dcp1 12 rl1 ?low? terminal of dcp1 13 rh1 ?high? terminal of dcp1 14 a0 device address for the i 2 c interface 15 a1 device address for the i 2 c interface 16 vcc power supply pin 17 d.n.c. do not connect 18 rh0 ?high? terminal of dcp0 19 rl0 ?low? terminal of dcp0 20 rw0 ?wiper? terminal of dcp0 ISL90840
3 fn8086.0 july 27, 2005 absolute maximum ratings recommended operating conditions storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage at any digital interface pin with respect to gnd . . . . . . . . . . . . . . . . . . . . . . -0.3v to v cc +0.3 v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v voltage at any dcp pin with respect to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v cc lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300c i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma latchup . . . . . . . . . . . . . . . . . . . . . . . . . . class ii, level b at +85c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2kv human body model industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v power rating of each dcp . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mw wiper current of each dcp . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0ma caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. analog specifications over recommended operating conditi ons unless otherwise stated. symbol parameter test conditions min typ (note 1) max unit r total r h to r l resistance w option 10 k ? u option 50 k ? r h to r l resistance tolerance -20 +20 % r w wiper resistance v cc = 3.3v @ 25c, wiper current = v cc /r total 70 200 ? c h /c l /c w potentiometer capacitance (note 15) 10/10/25 pf i lkgdcp leakage on dcp pins (note 15) voltage at pin from gnd to v cc 0.1 1 a voltage divider mode (0v @ r l i; v cc @ r h i; measured at r w i, unloaded; i = 0, 1, 2, or 3) inl (note 6) integral non-linearity -1 1 lsb (note 2) dnl (note 5) differential non-linearity monotonic over all tap positions -0.5 0.5 lsb (note 2) zserror (note 3) zero-scale error w option 0 1 7 lsb (note 2) u option 0 0.5 2 fserror (note 4) full-scale error w option -7 -1 0 lsb (note 2) u option -2 -1 0 v match (note 7) dcp to dcp matching any two dcps at same tap position, same voltage at all r h terminals, and same voltage at all r l terminals -2 2 lsb (note 2) tc v (note 8) ratiometric temperature coefficient dcp register set to 80 hex 4 ppm/c resistor mode (measurements between r w i and r l i with r h i not connected, or between r w i and r h i with r l i not connected. i = 0, 1, 2 or 3) rinl (note 12) integral non-linearity dcp register set between 20 hex and ff hex; monotonic over all tap positions -1 1 mi (note 9) rdnl (note 11) differential non-linearity -0.5 0.5 mi (note 9) roffset (note 10) offset w option 0 1 7 mi (note 9) u option 0 0.5 2 mi (note 9) r match (note 13) dcp to dcp matching any two dcps at the same tap position with the same terminal voltages -2 2 mi (note 9) tc r (note 14) resistance temperature coefficient dcp register set between 20 hex and ff hex 45 ppm/c ISL90840
4 fn8086.0 july 27, 2005 operating specifications over the recommended operating condi tions unless otherwise specified. symbol parameter test conditions min typ (note 1) max unit i cc1 v cc supply current (volatile write/read) f scl = 400khz; sda = open; (for i 2 c, active, read and write states) 1ma i sb v cc current (standby) v cc = +5.5v, i 2 c interface in standby state 5 a v cc = +3.6v, i 2 c interface in standby state 2 a i lkgdig leakage current, at pins a0, a1, a2, sda, and scl voltage at pin from gnd to v cc -10 10 a t dcp (note 15) dcp wiper response time scl falling edge of last bit of dcp data byte to wiper change 1s serial interface specs v il a2, a1, a0, sda, and scl input buffer low voltage -0.3 0.3*v cc v v ih a2, a1, a0, sda, and scl input buffer high voltage 0.7*v cc v cc +0.3 v hysteresis (note 15) sda and scl input buffer hysteresis 0.05* v cc v v ol (note 15) sda output buffer low voltage, sinking 4ma 00.4v cpin (note 15) a2, a1, a0, sda, and scl pin capacitance 10 pf f scl scl frequency 400 khz t in (note 15) pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed 50 ns t aa (note 15) scl falling edge to sda output data valid scl falling edge crossing 30% of v cc , until sda exits the 30% to 70% of v cc window 900 ns t buf (note 15) time the bus must be free before the start of a new transmission sda crossing 70% of v cc during a stop condition, to sda crossing 70% of v cc during the following start condition 1300 ns t low clock low time measured at the 30% of v cc crossing 1300 ns t high clock high time measured at the 70% of v cc crossing 600 ns t su:sta start condition setup time scl ri sing edge to sda falling edge; both crossing 70% of v cc 600 ns t hd:sta start condition hold time from sd a falling edge crossing 30% of v cc to scl falling edge crossing 70% of v cc 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of v cc window, to scl rising edge crossing 30% of v cc 100 ns t hd:dat input data hold time from scl rising edge crossing 70% of v cc to sda entering the 30% to 70% of v cc window 0ns t su:sto stop condition setup time from scl rising edge crossing 70% of v cc , to sda rising edge crossing 30% of v cc 600 ns t hd:sto stop condition hod time for read, or volatile only write from sda rising edge to scl falling edge; both crossing 70% of v cc 600 ns t dh (note 15) output data hold time from scl falling edge crossing 30% of v cc , until sda enters the 30% to 70% of v cc window 0ns t r (note 15) sda and scl rise time from 30% to 70% of v cc 20 + 0.1 * cb 250 ns ISL90840
5 fn8086.0 july 27, 2005 sda vs scl timing a0, a1, and a2 pin timing t f (note 15) sda and scl fall time from 70% to 30% of v cc 20 + 0.1 * cb 250 ns cb (note 15) capacitive loading of sda or scl total on-chip and off-chip 10 400 pf rpu (note 15) sda and scl bus pull-up resistor off- chip maximum is determined by t r and t f for cb = 400pf, max is about 2~2.5k ? . for cb = 40pf, max is about 15~20k ? 1k ? t su:a a2, a1 and a0 setup time before start condition 600 ns t hd:a a2, a1 and a0 hold time after stop condition 600 ns operating specifications over the recommended operating condi tions unless otherwise specified. (continued) symbol parameter test conditions min typ (note 1) max unit t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r t hd:a scl sda in a0, a1, or a2 t su:a clk 1 start stop ISL90840
6 fn8086.0 july 27, 2005 notes: 1. typical values are for t a = 25c and 3.3v supply voltage. 2. lsb: [v(r w ) 255 ? v(r w ) 0 ] / 255. v(r w ) 255 and v(r w ) 0 are v(r w ) for the dcp register set to ff hex and 00 hex respectively. lsb is the incremental voltage when changing from one tap to an adjacent tap. 3. zs error = v(r w ) 0 / lsb. 4. fs error = [v(r w ) 255 ? v cc ] / lsb. 5. dnl = [v(r w ) i ? v(r w ) i-1 ] / lsb-1, for i = 1 to 255. i is the dcp register setting. 6. inl = v(r w ) i ? i - lsb ? v(r w ) for i = 1 to 255. 7. v match = [v(r w x) i ? v(r w y) i ] / lsb, for i = 0 to 255, x = 0 to 3 and y = 0 to 3. 8. for i = 16 to 240 decimal, t = -40c to 85c. max( ) is the maximum value of the wiper voltage and min ( ) is the minimum value of the wiper voltage over the temperature range. 9. mi = | r 255 ? r 0 | / 255. r 255 and r 0 are the measured resistances for the dcp register set to ff hex and 00 hex respectively. 10. roffset = r 0 / mi, when measuring between r w and r l . roffset = r 255 / mi, when measuring between r w and r h . 11. rdnl = (r i ? r i-1 ) / mi, for i = 32 to 255. 12. rinl = [r i ? (mi ? i) ? r 0 ] / mi, for i = 32 to 255. 13. r match = (r i,x ? r i,y ) / mi, for i = 0 to 255, x = 0 to 3 and y = 0 to 3. 14. for i = 32 to 255, t = -40c to 85c. max( ) is the maximum value of the resistance and min ( ) is the minimum value of the resistance over the temperature range. 15. this parameter is not 100% tested. tc v max v rw () i () min v rw () i () ? max v rw () i () min v rw () i () + [] 2 ? --------------------------------------------------------------------------------------------- - 10 6 125c ---------------- - = tc r max ri () min ri () ? [] max ri () min ri () + [] 2 ? --------------------------------------------------------------- - 10 6 125c ---------------- - = typical performance curves figure 1. wiper resistance vs tap position [i(rw) = v cc / r total ] for 50k ? (u) figure 2. standby i cc vs v cc v cc =2.7, t=-40c v cc =2.7, t=+25c v cc =2.7, t=+85c v cc = 5.5, t=+85c v cc =5.5, t=+25c v cc =5.5, t=-40c 0 50 100 150 200 250 tap position (decimal) 160 140 120 100 80 60 40 20 0 wiper resistance ( ? ) -40c +85c +25c 2.7 3.2 3.7 4.2 4.7 5.2 v cc (v) 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0 standby i cc (a) 0.2 ISL90840
7 fn8086.0 july 27, 2005 figure 3. dnl vs tap position in voltage divider mode for 10k ? (w) figure 4. inl vs tap position in voltage divider mode for 10k ? (w) figure 5. zserror vs temperature for 50k ? (w) figure 6. fserror vs temperature for 50k ? (w) figure 7. dnl vs tap position in rheostat mode for 50k ? (u) figure 8. inl vs tap position in rheostat mode for 50k ? (u) typical performance curves (continued) v cc =2.7, t=-40c v cc =5.5, t=-40c v cc =2.7, t=+25c v cc =5.5, t=+25c v cc =2.7, t=+85c v cc =5.5, t=+85c 0 50 100 150 200 250 tap position (decimal) 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 dnl (lsb) v cc =5.5, t=-40c v cc =2.7, t=-40c v cc =2.7, t=+25c v cc =2.7, t=+85c v cc =5.5, t=+85c 0 50 100 150 200 250 tap position (decimal) 0.3 0.2 0.1 0 -0.1 -0.2 0.3 inl (lsb) 5.5v 2.7v -40 -20 20 40 60 80 temperature (c) 0.4 0.35 0.3 0.25 0.2 0.15 zserror (lsb) 0 v cc =5.5v v cc =2.7v -40 -20 20 40 60 80 temperature (c) 0 -0.2 -0.4 -0.6 -0.8 -1 fserror (lsb) 0 v cc =2.7, t=-40c v cc =5.5, t=-40c v cc =5.5, t=+25c v cc =5.5, t=+85c v cc =2.7, t=+25c v cc =2.7, t=+85c 32 82 132 182 232 tap position (decimal) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 dnl (lsb) v cc =2.7, v cc =2.7, t=+25c v cc =2.7, t=+85c v cc =5.5, t=+25c v cc =5.5, t=-40c v cc =5.5, t=+85c 32 82 132 182 232 tap position (decimal) 0.5 0.1 -0.3 -0.5 inl (lsb) -0.1 0.3 t=-40c ISL90840
8 fn8086.0 july 27, 2005 figure 9. end to end r total % change vs temperature for 50k ? (w) figure 10. tc for voltage divider mode in ppm for 50k ? (w) figure 11. tc for rheostat mode in ppm for 50k ? (w) figure 12. frequency response (2.2mhz) figure 13. midscale glitch, code 80h to 7fh (wiper 0) figure 14. large signal settling time typical performance curves (continued) 2.7v 5.5v -40 -20 20 40 60 80 temperature (c) 1.5 1 0.5 0 -0.5 -1.5 end to end r total change (%) 0 -1 32 82 132 182 232 tap position (decimal) 20 10 -10 -20 tc (ppm/c) 0 32 82 132 182 232 tap position (decimal) 35 5 -15 -25 tc (ppm/c) -5 25 15 tap position = mid point r total =9.4k output input wiper movement mid point from 80h to 7fh signal at wiper (wiper unloaded) scl signal at wiper (wiper uploaded movement from ffh to 00h ISL90840
9 fn8086.0 july 27, 2005 principles of operation the ISL90840 is an integrated circuit incorporating four dcps with their associated registers, and an i 2 c serial interface providing direct communication between a host and the potentiometers. dcp description each dcp is implemented with a combination of resistor elements and cmos switches. the physical ends of each dcp are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l pins). the r w pin of each dcp is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. the position of the wiper terminal within the dcp is controlled by an 8-bit volatile wiper register (wr). each dcp has its own wr. when the wr of a dcp contains all zeroes (wr<7:0>: 00h), its wiper terminal (r w ) is closest to its ?low? terminal (r l ). when the wr of a dcp contains all ones (wr<7:0>: ffh), its wiper terminal (r w ) is closest to its ?high? terminal (r h ). as the value of the wr increases from all zeroes (00h) to all ones (255 decimal), the wiper moves monotonically from the position closest to r l to the closest to r h . at the same time, the resistance between r w and r l increases monotonically, while the resistance between r h and r w decreases monotonically. while the ISL90840 is being powered up, all four wrs are reset to 80h (128 decimal), which locates r w roughly at the center between r l and r h . the wrs can be read or written to directly using the i 2 c serial interface as described in the following sections. the i 2 c interface address byte has to be set to 00h, 01h, 02h, and 03h to access the wr of dcp0, dcp1, dcp2, and dcp3 respectively i 2 c serial interface the ISL90840 supports a bidirectional bus oriented protocol. the protocol defines any devic e that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive operatio ns. therefore, the ISL90840 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. protocol conventions data states on the sda line must change only during scl low periods. sda state cha nges during scl high are reserved for indicating start and stop conditions (see figure 15). on power-up of the ISL90840 the sda pin is in the input mode. all i 2 c interface operations must begin with a start condition, which is a high to low transition of sda while scl is high. the ISL90840 continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 15). a start condition is ignored during the power- up of the device. all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 15). a stop condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. an ack, acknowledge, is a software convention used to indicate a successful data transfer. the transmitting device, either master or slave, releases the sda bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data (see figure 16). the ISL90840 responds with an ack after recognition of a start condition followed by a valid identification byte, and once again after successful rece ipt of an address byte. the ISL90840 also responds with an ack after receiving a data byte of a write operation. th e master must respond with an ack after receiving a data byte of a read operation a valid identification byte cont ains 0101 as the four msbs, and the following three bits matching the logic values present at pins a2, a1, and a0. the lsb is the read/write bit. its value is ?1? for a read operation, and ?0? for a write operation (see table 1). table 1. identification byte format 0101a2a1a0r/w (msb) (lsb) logic values at pins a2, a1, and a0 respectively ISL90840
10 fn8086.0 july 27, 2005 sda scl start data data stop stable change data stable figure 15. valid data changes, start, and stop conditions sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance figure 16. acknowledge response from receiver s t a r t s t o p identification byte address byte data byte a c k signals from the master signals from the ISL90840 a c k 0 0 0 11 a c k write signal at sda 0000 a0 a1 a2 00 00 figure 17. byte write sequence signals from the master signals from the slave signal at sda s t a r t identification byte with r/w =0 address byte a c k a c k 00 0 11 s t o p a c k 0 1 0 11 identification byte with r/w =1 a c k s t a r t last read data byte first read data byte a c k 0 000 00 a0 a1 a2 a0 a1 a2 figure 18. read sequence ISL90840
11 fn8086.0 july 27, 2005 write operation a write operation requires a start condition, followed by a valid identification byte, a valid address byte, a data byte, and a stop condition. after each of the three bytes, the ISL90840 responds with an ack. at this time, the device enters its standby state (see figure 17). read operation a read operation consist of a th ree byte instruction followed by one or more data bytes (see figure 18). the master initiates the operation issuing the following sequence: a start, the identification byte with the r/w bit set to ?0?, an address byte, a second start, and a second identification byte with the r/w bit set to ?1?. after each of the three bytes, the ISL90840 responds with an ack. then the ISL90840 transmits data bytes as long as the master responds with an ack during the scl cycle follo wing the eighth bit of each byte. the master terminates the read operation (issuing a stop condition) following the last bit of the last data byte (see figure 18). the data bytes are from the registers indicated by an internal pointer. this pointer initial value is determined by the address byte in the read operation instruction, and increments by one during transmission of each data byte. after reaching the memory location 03h, the pointer ?rolls over? to 00h, and the device continues to output data for each ack received. ISL90840
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8086.0 july 27, 2005 ISL90840 packaging information note: all dimensions in inches (in parentheses in millimeters). 20-lead plastic, tsso p, package code v20 see detail ?a? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .252 (6.4) .260 (6.6) .002 (.05) .006 (.15) .041 (1.05) .0075 (.19) .0118 (.30) 0 - 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)

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